Many data processing operations in a computer system involve the movement of large amounts of data. Some of these data movements, including those involving various virtual memory or cache memory operations, involve the movement of data between various memories, generally random access memories, within the system, while other operations involve receiving or transmitting data through appropriate serial, parallel or other ports to system peripherals, which, for purposes of this invention, are considered to be various input/outputs (I/O) for the system. Such I/Os include, but are by no means limited to, printers, displays, modems, disc drives, fixed or variable length packetized data channels such as Ethernet, HDLC or token ring, optical disc drive, floppy drive, etc. An external processor may also require access to at least a selected portion of a system memory. Transfers of data between a system peripheral and a system memory, or between system memories, is complicated by the fact that the peripheral/memories frequently operate at different speeds, requiring buffering of data to effect efficient transfer, and that the peripherals/memories may have different format protocols.
In current systems, the burden of controlling the transfer of data between system memories and between peripherals and a system memory generally falls on the system processor. In some applications, the processor can spend a majority of its time handling such memory transfers, significantly reducing the capacity of the processor to perform other functions. The burden on the processor of controlling memory accesses thus significantly reduces the processing speed and efficiency of a given computer system and results in a significant reduction in the volume of work which the processor can perform. While various direct memory access (DMA) controllers have been proposed for reducing the DMA burden on a system processor, these controllers have generally been useful for only a single channel (i.e., the interfacing of a memory in a single direction with a peripheral or with another system memory) and have therefore dealt with only a portion of the problem. In order to deal with all modes of data transfer in a given system, a separate DMA controller of these types is required for each channel. Since a system may contain ten or more channels, existing controllers require significant circuitry dedicated to the DMA function, resulting in system boards of a size and cost which may not be acceptable for many applications.
A need therefore exists for an improved DMA controller which is capable of independently or substantially independently handling all, or at least substantially all, transfers of data between system memories, and between various peripherals and system memory with minimum processor involvement, thereby freeing the processor from the burden of performing DMA functions, and permitting dramatic increases in the volume of work available from the processor, without requiring significant system circuitry for performing the DMA function so as to minimize both the size and cost burden of this function.
Another problem in performing DMA functions is that memory buffers are typically of a fixed size, while data coming in from various packetized data channels, such as Ethernet or HDLC, can be of variable length. Normally the buffer length in the memory for receiving such variable length packetized data has to be large enough to receive the largest packets, which packets may be many times the size of the smallest packets transmitted, for example, 8 to 16 times the size of the smallest packets. This means that significant memory space is generally wasted when variable length packetized data is transferred into memory and that far more memory space must be allocated to receiving such data that would be the case if such variable length data where more efficiently stored. However, the housekeeping burden in more efficiently storing such variable length data has heretofore been such that, in most applications, no effort is made to more efficiently store such data. In the rare situations where such efforts are made, the added processing burden involved in doing such transfers further reduces processor availability for performing other functions.
A need therefore also exists for a DMA controller which facilitates the more efficient storage of variable length packetized data in system memory without requiring substantial processing, and in particular, with little if any added processing burden on the system processor.